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EMIF07-LCD02F3
7-line IPADTM, EMI filter and ESD protection for LCD and cameras
Features

EMI symmetrical (I/O) low-pass filter High efficiency in EMI filtering Lead-free package Very low PCB space occupation: 1.42 mm x 1.42 mm Very thin package: 0.65 mm High efficiency in ESD suppression High reliability offered by monolithic integration High reduction of parasitic elements through integration and wafer level packaging Figure 1.
5
O1
Flip Chip (18 bumps)
Pin layout (bump side)
4
O2
3
GND
2
I1
1
I2 I3
Complies with the following standards
A B C D
IEC61000-4-2 level 4 on inputs and outputs: - 15 kV (air discharge) - 8 kV (contact discharge) MIL STD 883E - Method 3015-6 Class 3
O3 O4 O6 O5 O7
GND
GND
I4 I6
I5 I7
GND
Applications
Where EMI filtering in ESD sensitive equipment is required:

Figure 2.
Device configuration
Low-pass Filter
LCD for mobile phones Computers and printers Communication systems MCU boards
GND Input
Output
Description
The EMIF07-LCD02F3 is a 7-line highly integrated device designed to suppress EMI/RFI noise in all systems subjected to electromagnetic interference. The EMIF07 Flip Chip packaging means the package size is equal to the die size. This filter includes ESD protection circuitry, which prevents damage to the protected device when subjected to ESD surges up 15 kV.
GND
GND
Ri/o = 70 Cline = 30 pF
TM: IPAD is a trademark of STMicroelectronics. April 2008 Rev 2 1/8
www.st.com 8
Characteristics
EMIF07-LCD02F3
1
Characteristics
Table 1.
Symbol Tj Top Tstg
Absolute maximum ratings (Tamb = 25 C)
Parameter and test conditions Maximum junction temperature Operating temperature range Storage temperature range Value 125 -40 to +85 -55 to 150 Unit C C C
Table 2.
Symbol VBR IRM VRM VCL IPP RI/O Cline Symbol VBR IRM R2 Cline
Electrical characteristics (Tamb = 25 C)
Parameters Breakdown voltage Leakage current @ VRM Stand-off voltage Clamping voltage Peak pulse current Series resistance between input and output Input capacitance per line Test conditions IR = 1 mA VRM = 3 V Tolerance 20% Vline = 0 V, VOSC = 30 mV, F =1 MHz Min 6 Typ 8 50 70 30 Max 10 200 Unit V nA pF
IPP VCL VBR VRM IRM IR VF V I
IF
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EMIF07-LCD02F3
Characteristics
Figure 3.
0.00
S21(dB) all lines attenuation Figure 4. measurement and Aplac simulation
0.00 dB -10.00 -20.00 -30.00
Analog cross talk measurement
-10.00
-20.00
-40.00 -50.00
-30.00
-60.00
-40.00
-70.00 -80.00
-50.00 100.0k
-90.00
1.0M Line 1 Line 3 Line 5 Line 7 10.0M 100.0M Line 2 Line 4 Line 6 1.0G
-100.00 100.0k
1.0M
10.0M f/Hz
100.0M Xtalk 1/2
1.0G
Figure 5.
Voltages when IEC61000-4-2 (+15 kV air discharge) applied to input pin
Figure 6.
Voltages when IEC61000-4-2 (-15 kV air discharge) applied to input pin
Input 10V/d
Input 10V/d
Output 10V/d
Output 10V/d
100ns/d
100ns/d
Figure 7.
Line capacitance versus applied voltage
Cline (pF)
30 25 20 15 10 5
Vline (V)
0 0 1 2 3 4 5 6
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Application information
EMIF07-LCD02F3
2
Application information
Figure 8. Aplac model
Lbump I1 Rbump Rline Rbump Lbump O1
MODEL = D1
MODEL = D2
bulk
bulk MODEL = D3
Rbump Cbump Cbump Lbump
Rbump Cbump Lbump
Rbump Cbump Lbump
Rbump
Lbump
Rgnd Lgnd
Rgnd Lgnd
Rgnd Lgnd
Rgnd Lgnd
Figure 9.
Aplac parameters
aplacvar Rline 70 aplacvar C_d1 15p aplacvar C_d2 15p aplacvar C_d3 600p aplacvar Ls 950pH aplacvar Rs 150m aplacvar Lbump 50pH aplacvar Rbump 20m aplacvar Cbump 150f aplacvar Lgnd 50pH aplacvar Rgnd 100m aplacvar Rsub 10m
Diode D1 BV=7 IBV=1m CJO=C_d1 M=0.28 RS=0.1 VJ=0.6 TT=100n
Diode D2 BV=7 IBV=1m CJO=C_d2 M=0.28 RS=0.1 VJ=0.6 TT=100n
Diode D3 BV=7 IBV=1m CJO=C_d3 M=0.28 RS=0.01 VJ=0.6 TT=100n
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EMIF07-LCD02F3
Ordering information scheme
3
Ordering information scheme
Figure 10. Ordering information scheme
EMIF
EMI Filter Number of lines Information x = resistance value (Ohms) z = capacitance value / 10(pF) or 3 letters = application 2 digits = version Package F = Flip Chip 3 = Lead-free, pitch = 400 m, bump = 255 m
yy
-
xxx zz
F3
4
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. Figure 11. Package dimensions
400 m 40
400 m 40 255 m 40 605 m 55
185 m
1.97 mm 30m
185 m
1.57 mm 30 m
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Ordering information
EMIF07-LCD02F3
Figure 12. Footprint
Copper pad Diameter: 220 m recommended 260 m maximum Solder mask opening: 300 m minimum
Figure 13. Marking
Dot, ST logo xx = marking z = manufacturing location yww = datecode (y = year ww = week)
E
Solder stencil opening: 220 m recommended
xxz y ww
Dot identifying Pin A1 location 4 0.1 O 1.5 0.1
1.75 0.1
Figure 14. Flip Chip tape and reel specification
3.5 0.1
1.71
8 0.3
STE
STE
STE
xxz yww
xxz yww
xxz yww
2.08
0.69 0.05
4 0.1
All dimensions in mm
User direction of unreeling
Note:
More information is available in the application notes: AN2348: "STMicroelectronics 400 micro-metre Flip Chip : Package description and recommendation for use" AN1751: "EMI filters: Recommendations and measurements"
5
Ordering information
Table 3. Ordering information
Marking GX Package Flip Chip Weight 3.9 mg Base qty 5000 Delivery mode Tape and reel 7"
Order code EMIF07-LCD02F3
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EMIF07-LCD02F3
Revision history
6
Revision history
Table 4.
Date 12-Sep-2005 28-Apr-2008
Document revision history
Revision 1 2 First issue. Updated ECOPACK statement. Updated Figure 10, Figure 11 and Figure 14. Reformatted to current standards. Changes
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EMIF07-LCD02F3
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